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dir · 2018-11-07 23:41:36

dir
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Topic: Jitter issue on the INT clock

I was looking for behaviour of some digital transports on optical input of RME ADI-2 Pro FS.
I was notice a significant jitter raises when I set clock to INT + SRC SPDIF. It even worse than Airport Express as master.
Arta and MusicScope software are used as measurement software in 24 and 16bit modes.

Airport Express (Clock SPDIF, SRC-off):

Airport Express (Clock SPDIF, SRC-on):

Airport Express (Clock INT, SRC-on):

It looks same on other digital transports. Its a wrong mode maybe or I doing something wrong?

MC · 2018-11-09 15:26:10

MC
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Re: Jitter issue on the INT clock

I have no clue what is going wrong here, and I can not reproduce these measurements.

Here is an iPad playing back the 11.025 kHz sine via a UCX in CC mode over SPDIF into the ADI-2 Pro. With external clock or SRC off the measurement looks perfect. This pic is the worst I could produce.

I also still have no clue what all this is good for, or what it is supposed to show.

Regards
Matthias Carstens
RME

dir · 2018-11-09 20:33:02

dir
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Re: Jitter issue on the INT clock

I was got all these pictures from SPDIF-in on ASIO inputs, not analog

Is it possible that I just have non-FS version with higher jitter? Because my paper box stll have old design without FS signature

MC · 2018-11-10 02:42:00

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Re: Jitter issue on the INT clock

Obviously my measurement is also SPDIF In, not analog (noise floor down at -170 dBFS with analog?).

If your front plate says FS then you have one. And your first two measurements look like that as well.

Regards
Matthias Carstens
RME

dir · 2018-11-11 12:09:11

dir
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Re: Jitter issue on the INT clock

Thank you for your feedback. It is understdood that your measuerments was made in digital domain.

I just want to understand the differences between the modes. As far as I understand, the SRC is a prerequisite mode when turning clock to Int? When I try to record the 11 kHz jitter tone in the (Clock INT, SRC-on) mode, the level begins to "float" as a modulation product. The status of the signal was changed to 24 bits on RME display, although 16 bits are supplied though AES-in. This is not all there is if clock was switch to AES and SRC was turn-off.

ADI-2 Remote v2.0 now available!

Jitter issue on the INT clock

Posts: 5

1 Topic by dir 2018-11-07 23:41:36 (edited by dir 2018-11-08 11:31:17)

Topic: Jitter issue on the INT clock

2 Reply by MC 2018-11-09 15:26:10

Re: Jitter issue on the INT clock

3 Reply by dir 2018-11-09 20:33:02 (edited by dir 2018-11-09 21:21:40)

Re: Jitter issue on the INT clock

4 Reply by MC 2018-11-10 02:42:00

Re: Jitter issue on the INT clock

5 Reply by dir 2018-11-11 12:09:11

Re: Jitter issue on the INT clock

Posts: 5